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? semiconductor components industries, llc, 2015 march, 2015 ? rev. 2 1 publication order number: amis?30532/d amis-30532 micro-stepping motor driver introduction the amis?30532 is a micro?stepping stepper motor driver for bipolar stepper motors. the chip is connected through i/o pins and an spi interface with an external microcontroller. it has an on?chip voltage regulator, reset?output and watchdog reset, able to supply peripheral devices. the amis?30532 contains a current?translation table and takes the next micro?step depending on the clock signal on the ?nxt? input pin and the status of the ?dir? (=direction) register or input pin. the chip provides a so?called ?speed and load angle? output. this allows the creation of stall detection algorithms and control loops based on load?angle to adjust torque and speed. it is using a proprietary pwm algorithm for reliable current control. the amis?30532 is implemented in i 2 t100 technology, enabling both high?voltage analog circuitry and digital functionality on the same chip. the chip is fully compatible with the automotive voltage requirements. the amis?30532 is ideally suited for general?purpose stepper motor applications in the automotive, industrial, medical, and marine environment. with the on?chip voltage regulator it further reduces the bom for mechatronic stepper applications. key features ? dual h?bridge for 2?phase stepper motors ? programmable peak?current up to 1.6 a continuous ? (3.0 a short time) using a 5?bit current dac ? on?chip cu rrent translator ? spi interface ? speed and load angle output ? seven step modes from full?step up to 32 micro?steps ? fully integrated current?sense ? pwm current control with automatic selection of fast and slow decay ? low emc pwm with selectable voltage slopes ? active fly?back diodes ? full output protection and diagnosis ? thermal warning and shutdown ? compatible with 5 v and 3.3 v microcontrollers ? integrated 5 v regulator to supply external microcontroller ? integrated reset function to reset external microcontroller ? integrated watchdog function ? these devices are pb?free and are rohs compliant* ?output current level may be limited by ambient temperature and heat sinking. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. see detailed ordering and shipping information in the package dimensions section on page 27 of this data sheet. ordering information www. onsemi.com nqfp?32, 7x7 case 560aa marking diagram a = assembly location wl = wafer lot yy = year ww = work week g = pb?free designator ccccc = country of assembly
amis?30532 www. onsemi.com 2 block diagram temp . sense spi otp timebase por di do cs clk nxt sla dir err band? gap load angle amis?30532 logic & registers chargepump t r a n s l a t o r vreg clr vbb p w m i? sense emc p w m i? sense emc vdd gnd motxp motxn motyp motyn cpn cpp vcp por/wd figure 1. block diagram amis?30532 table 1. pin list and description name pin description type equivalent schematic gnd 1 ground supply di 2 spi data in digital input type 2 clk 3 spi clock input digital input type 2 nxt 4 next micro?step input digital input type 2 dir 5 direction input digital input type 2 err 6 error output (open drain) digital output type 4 sla 7 speed load angle output analog output type 5 / 8 no function (to be left open in normal operation) cpn 9 negative connection of charge pump capacitor high voltage cpp 10 positive connection of charge pump capacitor high voltage vcp 11 charge?pump filter?capacitor high voltage clr 12 ?clear? = chip reset input digital input type 1 cs 13 spi chip select input digital input type 2 vbb 14 high voltage supply input supply type 3 motyp 15, 16 negative end of phase y coil output driver output gnd 17, 18 ground, heat sink supply motyn 19, 20 positive end of phase y coil output driver output motxn 21, 22 positive end of phase x coil output driver output gnd 23, 24 ground, heat sink supply motxp 25, 26 negative end of phase x coil output driver output vbb 27 high voltage supply input supply type 3 / 30 no function (to be left open in normal operation) por /wd 28 power?on?reset and watchdog reset output (open drain) digital output type 2 tst0 29 test pin input (to be tied to ground in normal operation) digital input do 31 spi data output (open drain) digital output type 4 vdd 32 logic supply output (needs external decoupling capacitor) supply type 6
amis?30532 www. onsemi.com 3 pin description 1 2 3 5 4 6 7 8 24 23 22 20 21 19 18 17 9 101112131415 16 32 31 30 29 28 27 26 25 do di cpn motxp gnd gnd motxp motyn por/wd motyp clk vdd clr cs dir nxt sla amis ?30532 gnd gnd gnd motyn motxn motxn motyp vbb tst0 cpp vcp vbb figure 2. pin out amis?30532 err table 2. absolute maximum ratings symbol parameter min max unit v bb analog dc supply voltage (note 1) ?0.3 +40 v t st storage temperature ?55 +160 c t j junction temperature under bias (note 2) ?50 +175 c v esd electrostatic discharges on component level, all pins (note 3) ?2 +2 kv v esd electrostatic discharges on component level, hiv pins (note 4) ?8 +8 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. for limited time < 0.5 s. 2. circuit functionality not guaranteed. 3. human body model (100 pf via 1.5 k , according to jedec eia?jesd22?a114?b). 4. hiv = high voltage pins motxx, v bb , gnd; (100 pf via 1.5 k , according to jedec eia?jesd22?a114?b). table 3. thermal resistance package thermal resistance unit junction ? to ? exposed pad junction ? to ? ambient 1s0p board 2s2p board nqfp?32 0,95 60 30 k/w
amis?30532 www. onsemi.com 4 equivalent schematics following figure gives the equivalent schematics of the user relevant inputs and outputs. the diagrams are simplified representations of the circuits used. in rin 4k in 4k type 1: clr input type 2 : clk , di, csb , nxt , dir inputs . vdd vdd type 3: vdd and vbb power supply inputs vbb vbb out type 4: do and errb open drain outputs sla rout type 5: sla analog output figure 3. in? and output equivalent diagram package thermal characteristics the amis?30532 is available in a nqfp32 package. for cooling optimizations, the nqfp has an exposed thermal pad which has to be soldered to the pcb ground plane. the ground plane needs thermal vias to conduct the heat to the bottom layer. figure 3 gives an example for good power distribution solutions. for precise thermal cooling calculations the major thermal resistances of the device are given. the thermal media to which the power of the devices has to be given are: ? static environmental air (via the case) ? pcb board copper area (via the exposed pad) the thermal resistances are presented in table 5: dc parameters. the major thermal resistances of the device are the rth from the junction to the ambient (rthja) and the overall rth from the junction to exposed pad (rthjp). in table 5 below one can find the values for the rthja and rthjp, simulated according to jesd?51: the rthja for 2s2p is simulated conform jedec jesd?51 as follows: ? a 4?layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used ? board thickness is 1.46 mm (fr4 pcb material) ? the 2 signal layers: 70 m thick copper with an area of 5500 mm 2 copper and 20% conductivity ? the 2 power internal planes: 36 m thick copper with an area of 5500 mm 2 copper and 90% conductivity the rthja for 1s0p is simulated conform to jedec jesd?51 as follows: ? a 1?layer printed circuit board with only 1 layer ? board thickness is 1.46 mm (fr4 pcb material) ? the layer has a thickness of 70 m copper with an area of 5500 mm 2 copper and 20% conductivity
amis?30532 www. onsemi.com 5 ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? operating ranges define the limits for functional operation and parametric characteristics of the device. note that the functionality of the chip outside these operating ranges is not guaranteed. operating outside the recommended operating ranges for extended periods of time may affect device reliability. table 4. operating ranges symbol parameter min max unit v bb analog dc supply +6 +30 v t j junction temperature (note 5) ?40 +172 c 5. no more than 100 cumulative hours in life time above t tw .
amis?30532 www. onsemi.com 6 table 5. dc parameters (the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified) convention: currents flowing in the circuit are defined as positive. symbol pin(s) parameter remark/test conditions min typ max unit supply and voltage regulators v bb v bb nominal operating supply range 6 30 v i bb total current consumption (note 6) unloaded outputs 8 ma v dd v dd regulated output voltage 4.50 5 5.50 v i int internal load current (note 6) unloaded outputs 8 ma i load max output current (external and internal loads) 6 v < v bb < 8 v 20 ma 8 v < v bb < 30 v 50 ma i ddlim current limitation pin shorted to ground 150 ma i load_pd output current in powerdown 1 ma power?on?reset (por) v ddh v dd internal por comparator threshold v dd rising 4.0 4.25 4.4 v v ddl internal por comparator threshold v dd falling 3.68 v motordriver i mdmax,peak motxp motxn motyp motyn max current through motor coil in normal operation 3015 ma i mdmax,rms max rms current through coil in normal operation 2132 ma i mdabs absolute error on coil current ?10 10 % i mdrel error on current ratio i coilx / i coily ?7 7 % i set_tc1 temperature coefficient of coil cur- rent set?level, cur[4:0] = 0...27 ?40 c t j 160 c ?250 ppm/k i set_tc2 temperature coefficient of coil cur- rent set?level, cur[4:0] = 28...31 ?40 c t j 160 c ?460 ppm/k r hs on?resistance high?side driver, cur[4:0] = 0...31 (note 7) v bb = 12 v, t j = 27 c 0.35 v bb = 12 v, t j = 160 c 0.47 0.70 r ls3 on?resistance low?side driver, cur[4:0] = 23...31 (note 7) v bb = 12 v, t j = 27 c 0.35 v bb = 12 v, t j = 160 c 0.56 0.70 r ls2 on?resistance low?side driver, cur[4:0] = 16...22 (note 7) v bb = 12 v, t j = 27 c 0.65 v bb = 12 v, t j = 160 c 0.9 1.25 r ls1 on?resistance low?side driver, cur[4:0] = 9...15 (note 7) v bb = 12 v, t j = 27 c 1.25 v bb = 12 v, t j = 160 c 1.7 2.5 r ls0 on?resistance low?side driver, cur[4:0] = 0...8 (note 7) v bb = 12 v, t j = 27 c 2.5 v bb = 12 v, t j = 160 c 3.2 5.0 i mpd pulldown current hiz mode 5.0 ma digital inputs i leak di, clk nxt, dir clr, cs input leakage (note 8) t j = 160 c 1 a v inl logic low threshold 0 0.65 v v inh logic high threshold 2.35 v dd v r pd_clr clr internal pulldown resistor 120 300 k r pd_tst tst0 internal pulldown resistor 3 9 k 6. current with oscillator running, all analogue cells active, spi communication and nxt pulses applied. no floating inputs. par ameter guaranteed by design. 7. characterization data only 8. not valid for pins with internal pulldown resistor.
amis?30532 www. onsemi.com 7 table 5. dc parameters (the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified) convention: currents flowing in the circuit are defined as positive. symbol unit max typ min remark/test conditions parameter pin(s) digital outputs v ol do, err , por /wd logic low level open drain i ol = 5 ma 0.5 v thermal warning and shutdown t tw thermal warning 138 145 152 c t tsd thermal shutdown (notes 9 and 10) t tw + 20 c charge pump v cp vcp output voltage 6 v< v bb < 15 v 2*v bb ?1.5 v 15 v < v bb < 30 v v bb +8 v bb +11.5 v bb +15 v c buffer external buffer capacitor 180 220 470 nf c pump cpp cpn external pump capacitor 180 220 470 nf package thermal resistance value rth ja nqfp thermal resistance junction?to? ambient simulated conform jedec jesd?51, (2s2p) 30 k/w rth jp thermal resistance junction?to? exposed pad 0.95 k/w speed and load angle output v out sla output voltage range 0.2 v dd ? 0.2 v v off output offset sla pin slag = 0 ?50 50 mv slag = 1 ?30 30 mv g sla gain of sla pin = v bemf /v coil slag = 0 0.5 slag = 1 0.25 r out output resistance sla pin 0.23 1.0 k c load load capacitance sla pin 50 pf 9. no more than 100 cumulated hours in life time above t tw. 10. thermal shutdown is derived from thermal warning characterization data only.
amis?30532 www. onsemi.com 8 table 6. ac parameters (the ac parameters are given for v bb and temperature in their operating ranges) symbol pin(s) parameter remark/test conditions min typ max unit internal oscillator f osc frequency of internal oscillator 3.6 4.0 4.4 mhz motordriver f pwm motxx pwm frequency frequency depends only on internal oscillator 20.8 22.8 24.8 khz double pwm frequency 41.6 45.6 49.6 khz f d pwm jitter depth (note 11) 10 % f pwm tb rise motxx turn?on voltage slope, 10% to 90% emc[1:0] = 00 350 v/ s emc[1:0] = 01 250 v/ s emc[1:0] = 10 200 v/ s emc[1:0] = 11 100 v/ s tb fall motxx turn?off voltage slope, 90% to 10% emc[1:0] = 00 350 v/ s emc[1:0] = 01 250 v/ s emc[1:0] = 10 200 v/ s emc[1:0] = 11 100 v/ s digital outputs t h2l do err output fall?time from v inh to v inl capacitive load 400 pf and pullup resistor of 1.5 k 50 ns charge pump f cp cpn cpp charge pump frequency 250 khz t cpu motxx start?up time of charge pump (note 12) spec external components in table 8 5 ms clr function t clr clr hard reset duration time 100 s powerup t pu por / wd powerup time v bb = 12 v, i load = 50 ma, c load = 220 nf 110 s t por reset duration see figure 16 100 ms t rf reset filter time see figure 16 1.0 s watchdog t wdto por / wd watchdog time out interval 32 512 ms t wdpr prohibited watchdog acknowledge delay 2.0 ms nxt function t nxt_hi nxt nxt minimum, high pulse width see figure 5 2.0 s t nxt_hi nxt minimum, low pulse width see figure 5 2.0 s t dir_set nxt hold time, following change of dir see figure 5 0.5 s t dir_hold nxt hold time, before change of dir see figure 5 0.5 s 11. characterization data only 12. guaranteed by design
amis?30532 www. onsemi.com 9 ?? ?? ?? ?????????? ?????????? ?????????? figure 5. nxt?input timing diagram table 7. spi timing parameters symbol parameter min typ max unit t clk spi clock period 1 s t clk_high spi clock high time 100 ns t clk_low spi clock low time 100 ns t set_di di set up time, valid data before rising edge of clk 50 ns t hold_di di hold time, hold data after rising edge of clk 50 ns t csb_high cs high time 2.5 s t set_csb cs set up time, cs low before rising edge of clk 100 ns t set_clk clk set up time, clk low before rising edge of cs 100 ns figure 6. spi timing ??? ??? ??? ??????????? ??????????? ??????????? di clk t set _csb cs t clk t set_clk 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0. 2 v cc t clk_hi t clk _lo t set_di t hold_di valid
amis?30532 www. onsemi.com 10 typical application schematic figure 7. typical application schematic amis?30532 por/wd vcp cpp cpn clr c 7 err gnd cs clk di do nxt dir motxp motxn motyp motyn m 220 nf 100 nf c 5 v bat vdd vbb vbb 100 nf 220 nf 100 f c 2 c 3 c 6 c 1 100 nf 100 nf c 4 sla c 8 r 1 c d 1 r 2 r 3 r 4 amis?3053 2 2 15, 16 12 10 11 23 5 4 1 21, 22 18 3 17 19, 20 7 9 13 28 6 14 24 25, 26 27 tsto 29 31 32 table 8. external components list and description component function typ value tolerance unit c 1 v bb buffer capacitor (note 13) 100 ?20 +80% f c 2 , c 3 v bb decoupling block capacitor 100 ?20 +80% nf c 4 v dd buffer capacitor 100 20% nf c 5 v dd buffer capacitor 100 20% nf c 6 charge pump buffer capacitor 220 20% nf c 7 charge pump pumping capacitor 220 20% nf c 8 low pass filter sla 1 20% nf r 1 low pass filter sla 5.6 1% k r 2, r 3, r 4 pullup resistor open drain output 4.7 1% k d 1 optional reverse protection diode murd530 13. esr < 1 .
amis?30532 www. onsemi.com 11 functional description h?bridge drivers a full h?bridge is integrated for each of the two stator windings. each h?bridge consists of two low?side and two high?side n?type mosfet switches. writing logic ?0? in bit disables all drivers (high?impedance). writing logic ?1? in this bit enables both bridges and current can flow in the motor stator windings. in order to avoid large currents through the h?bridge switches, it is guaranteed that the top? and bottom?switches of the same half?bridge are never conductive simultaneously (interlock delay). a two?stage protection against shorts on motor lines is implemented. in a first stage, the current in the driver is limited. secondly, when excessive voltage is sensed across the transistor, the transistor is switched?off. in order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. the output slope is defined by the gate?drain capacitance of output transistor and the (limited) current that drives the gate. there are two trimming bits for slope control (see spi control parameter overview emc[1:0]). the power transistors are equipped with so?called ?active diodes?: when a current is forced trough the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. this ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain?bulk diode of the transistor. depending on the desired current range and the micro?step position at hand, the r ds(on) of the low?side transistors will be adapted such that excellent current?sense accuracy is maintained. the r ds(on) of the high?side transistors remain unchanged, see table 5 dc parameters for more details. pwm current control a pwm comparator compares continuously the actual winding current with the requested current and feeds back the information to a digital regulation loop. this loop then generates a pwm signal, which turns on/off the h?bridge switches. the switching points of the pwm duty?cycle are synchronized to the on?chip pwm clock. the frequency of the pwm controller can be doubled and an artificial jitter can be added (see spi control parameter overview pwmj). the pwm frequency will not vary with changes in the supply voltage. also variations in motor?speed or load?conditions of the motor have no effect. there are no external components required to adjust the pwm frequency. automatic forward and slow?fast decay the pwm generation is in steady?state using a combination of forward and slow?decay. the absence of fast?decay in this mode, guarantees the lowest possible current?ripple ?by design?. for transients to lower current levels, fast?decay is automatically activated to allow high?speed response. the selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation. icoil 0 t forward & slow decay forward & slow decay fast decay & forward actual value set value t pwm figure 8. forward and slow/fast decay pwm
amis?30532 www. onsemi.com 12 automatic duty cycle adaptation in case the supply voltage is lower than 2*bemf, then the duty cycle of the pwm is adapted automatically to > 50% to maintain the requested average current in the coils. this process is completely automatic and requires no additional parameters for operation. the over?all current?ripple is divided by two if pwm frequency is doubled (see spi control parameter overview pwmf). actual value duty cycle <50% duty cycle >50% duty cycle < 50% t icoil set value t pwm figure 9. automatic duty cycle adaptation step translator and step mode the step translator provides the control of the motor by means of spi register stepmode: sm[2:0], spi register dircntrl, and input pins dir and nxt. it is translating consecutive steps in corresponding currents in both motor coils for a given step mode. one out of seven possible stepping modes can be selected through spi?bits sm[2:0] (see spi control parameter overview) . after power?on or hard reset, the coil?current translator is set to the default 1/32 micro?stepping at position ?0?. upon changing the step mode, the translator jumps to position 0* of the corresponding stepping mode. when remaining in the same step mode, subsequent translator positions are all in the same column and increased or decreased with 1. table 10 lists the output current versus the translator position. as shown in figure 10 the output current?pairs can be projected approximately on a circle in the (i x , i y ) plane. there are, however, two exceptions: uncompensated half step and full step. in these step modes the currents are not regulated to a fraction of i max but are in all intermediate steps regulated at 100%. in the (i x , i y ) plane the current?pairs are projected on a square. t able 9 list s the output current versus the translator position for these cases. table 9. square translator table for full step and uncompensated half step msp[6:0] stepmode ( sm[2:0] ) % of i max 101 110 coil x coil y uncompensated half?step full step 000 0000 0* ? 0 100 001 0000 1 1 100 100 010 0000 2 ? 100 0 011 0000 3 2 100 ?100 100 0000 4 ? 0 ?100 101 0000 5 3 ?100 ?100 110 0000 6 ? ?100 0 111 0000 7 0 ?100 100
amis?30532 www. onsemi.com 13 table 10. circular translator table msp[6:0] stepmode (sm[2:0]) % of i max 000 001 010 011 100 coil x coil y 1/32 1/16 1/8 1/4 1/2 000 0000 ?0? 0* 0* 0* 0* 0 100 000 0001 1 ? ? ? ? 3.5 98.8 000 0010 2 1 ? ? ? 8.1 97.7 000 0011 3 ? ? ? ? 12.7 96.5 000 0100 4 2 1 ? ? 17.4 95.3 000 0101 5 ? ? ? ? 22.1 94.1 000 0110 6 3 ? ? ? 26.7 93 000 0111 7 ? ? ? ? 31.4 91.8 000 1000 8 4 2 1 ? 34.9 89.5 000 1001 9 ? ? ? ? 38.3 87.2 000 1010 10 5 ? ? ? 43 84.9 000 1011 11 ? ? ? ? 46.5 82.6 000 1100 12 6 3 ? ? 50 79 000 1101 13 ? ? ? ? 54.6 75.5 000 1110 14 7 ? ? ? 58.1 72.1 000 1111 15 ? ? ? ? 61.6 68.6 001 0000 16 8 4 2 1 65.1 65.1 001 0001 17 ? ? ? ? 68.6 61.6 001 0010 18 9 ? ? ? 72.1 58.1 001 0011 19 ? ? ? ? 75.5 54.6 001 0100 20 10 5 ? ? 79 50 001 0101 21 ? ? ? ? 82.6 46.5 001 0110 22 11 ? ? ? 84.9 43 001 0111 23 ? ? ? ? 87.2 38.3 001 1000 24 12 6 3 ? 89.5 34.9 001 1001 25 ? ? ? ? 91.8 31.4 001 1010 26 13 ? ? ? 93 26.7 001 1011 27 ? ? ? ? 94.1 22.1 001 1100 28 14 7 ? ? 95.3 17.4 001 1101 29 ? ? ? ? 96.5 12.7 001 1110 30 15 ? ? ? 97.7 8.1 001 1111 31 ? ? ? ? 98.8 3.5 010 0000 32 16 8 4 2 100 0 010 0001 33 ? ? ? ? 98.8 ?3.5 010 0010 34 17 ? ? ? 97.7 ?8.1 010 0011 35 ? ? ? ? 96.5 ?12.7 010 0100 36 18 9 ? ? 95.3 ?17.4 010 0101 37 ? ? ? ? 94.1 ?22.1 010 0110 38 19 ? ? ? 93 ?26.7 010 0111 39 ? ? ? ? 91.8 ?31.4 010 1000 40 20 10 5 ? 89.5 ?34.9 010 1001 41 ? ? ? ? 87.2 ?38.3 010 1010 42 21 ? ? ? 84.9 ?43 010 1011 43 ? ? ? ? 82.6 ?46.5 010 1100 44 22 11 ? ? 79 ?50 010 1101 45 ? ? ? ? 75.5 ?54.6 010 1110 46 23 ? ? ? 72.1 ?58.1 010 1111 47 ? ? ? ? 68.6 ?61.6 011 0000 48 24 12 6 3 65.1 ?65.1 011 0001 49 ? ? ? ? 61.6 ?68.6 011 0010 50 25 ? ? ? 58.1 ?72.1 011 0011 51 ? ? ? ? 54.6 ?75.5 011 0100 52 26 13 ? ? 50 ?79 011 0101 53 ? ? ? ? 46.5 ?82.6 011 0110 54 27 ? ? ? 43 ?84.9 011 0111 55 ? ? ? ? 38.3 ?87.2 011 1000 56 28 14 7 ? 34.9 ?89.5 011 1001 57 ? ? ? ? 31.4 ?91.8 011 1010 58 29 ? ? ? 26.7 ?93 011 1011 59 ? ? ? ? 22.1 ?94.1 011 1100 60 30 15 ? ? 17.4 ?95.3 011 1101 61 ? ? ? ? 12.7 ?96.5 011 1110 62 31 ? ? ? 8.1 ?97.7 011 1111 63 ? ? ? ? 3.5 ?98.8
amis?30532 www. onsemi.com 14 table 11. circular translator table (continued) msp[6:0] stepmode (sm[2:0]) % of i max 000 001 010 011 100 coil x coil y 1/32 1/16 1/8 1/4 1/2 100 0000 64 32 16 8 4 0 ?100 100 0001 65 ? ? ? ? ?3.5 ?98.8 100 0010 66 33 ? ? ? ?8.1 ?97.7 100 0011 67 ? ? ? ? ?12.7 ?96.5 100 0100 68 34 17 ? ? ?17.4 ?95.3 100 0101 69 ? ? ? ? ?22.1 ?94.1 100 0110 70 35 ? ? ? ?26.7 ?93 100 0111 71 ? ? ? ? ?31.4 ?91.8 100 1000 72 36 18 9 ? ?34.9 ?89.5 100 1001 73 ? ? ? ? ?38.3 ?87.2 100 1010 74 37 ? ? ? ?43 ?84.9 100 1011 75 ? ? ? ? ?46.5 ?82.6 100 1100 76 38 19 ? ? ?50 ?79 100 1101 77 ? ? ? ? ?54.6 ?75.5 100 1110 78 39 ? ? ? ?58.1 ?72.1 100 1111 79 ? ? ? ? ?61.6 ?68.6 101 0000 80 40 20 10 5 ?65.1 ?65.1 101 0001 81 ? ? ? ? ?68.6 ?61.6 101 0010 82 41 ? ? ? ?72.1 ?58.1 101 0011 83 ? ? ? ? ?75.5 ?54.6 101 0100 84 42 21 ? ? ?79 ?50 101 0101 85 ? ? ? ? ?82.6 ?46.5 101 0110 86 43 ? ? ? ?84.9 ?43 101 0111 87 ? ? ? ? ?87.2 ?38.3 101 1000 88 44 22 11 ? ?89.5 ?34.9 101 1001 89 ? ? ? ? ?91.8 ?31.4 101 1010 90 45 ? ? ? ?93 ?26.7 101 1011 91 ? ? ? ? ?94.1 ?22.1 101 1100 92 46 23 ? ? ?95.3 ?17.4 101 1101 93 ? ? ? ? ?96.5 ?12.7 101 1110 94 47 ? ? ? ?97.7 ?8.1 101 1111 95 ? ? ? ? ?98.8 ?3.5 110 0000 96 48 24 12 6 ?100 0 110 0001 97 ? ? ? ? ?98.8 3.5 110 0010 98 49 ? ? ? ?97.7 8.1 110 0011 99 ? ? ? ? ?96.5 12.7 110 0100 100 50 25 ? ? ?95.3 17.4 110 0101 101 ? ? ? ? ?94.1 22.1 110 0110 102 51 ? ? ? ?93 26.7 110 0111 103 ? ? ? ? ?91.8 31.4 110 1000 104 52 26 13 ? ?89.5 34.9 110 1001 105 ? ? ? ? ?87.2 38.3 110 1010 106 53 ? ? ? ?84.9 43 110 1011 107 ? ? ? ? ?82.6 46.5 110 1100 108 54 27 ? ? ?79 50 110 1101 109 ? ? ? ? ?75.5 54.6 110 1110 110 55 ? ? ? ?72.1 58.1 110 1111 111 ? ? ? ? ?68.6 61.6 111 0000 112 56 28 14 7 ?65.1 65.1 111 0001 113 ? ? ? ? ?61.6 68.6 111 0010 114 57 ? ? ? ?58.1 72.1 111 0011 115 ? ? ? ? ?54.6 75.5 111 0100 116 58 29 ? ? ?50 79 111 0101 117 ? ? ? ? ?46.5 82.6 111 0110 118 59 ? ? ? ?43 84.9 111 0111 119 ? ? ? ? ?38.3 87.2 111 1000 120 60 30 15 ? ?34.9 89.5 111 1001 121 ? ? ? ? ?31.4 91.8 111 1010 122 61 ? ? ? ?26.7 93 111 1011 123 ? ? ? ? ?22.1 94.1 111 1100 124 62 31 ? ? ?17.4 95.3 111 1101 125 ? ? ? ? ?12.7 96.5 111 1110 126 63 ? ? ? ?8.1 97.7 111 1111 127 ? ? ? ? ?3.5 98.8
amis?30532 www. onsemi.com 15 i y i x 1/4 th micro step sm[2:0] = 011 step 1 start = 0 step 2 step 3 uncompensated half step sm[2:0] = 101 i y i x start = 0 step 1 step 2 step 3 full step sm[2:0] = 110 i y i x start = 0 step 1 step 2 step 3 figure 10. translator table: circular and square direction the direction of rotation is selected by means of following combination of the dir input pin and the spi?controlled direction bit . (see table 14 spi control parameter overview) nxt input changes on the nxt input will move the motor current one step up/down in the translator table (even when the motor is disabled < moten>=0 >). depending on the nxt?polarity bit (see table 14 spi control parameter overview), the next step is initiated either on the rising edge or the falling edge of the nxt input. translator position the translator position msp[6:0] can be read in spi status register 3 (see table 15 sr3). this is a 7?bit number equivalent to the 1/32 th micro?step from t able 10: circular translator table. the translator position is updated immediately following a nxt trigger. nxt update translator position update translator position figure 11. translator position timing diagram synchronization of step mode and nxt input when step mode is re?programmed to another resolution (figure 12), then this is put in effect immediately upon the first arriving ?nxt? input. if the micro?stepping resolution is increased, the coil currents will be regulated to the nearest micro?step, according to the fixed grid of the increased resolution. if however the micro?stepping resolution is decreased, then it is possible to introduce an offset (or phase shift) in the micro?step translator table. if the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro?stepping is proceeds according to the translator table. if the translator position is not shared both by the old and new resolution setting, then the micro?stepping proceeds with an offset relative to the translator table (see figure 12 right hand side).
amis?30532 www. onsemi.com 16 ix dir iy ix iy dir nxt1 nxt2 nxt3 nxt4 halfstep endpos 1/4 th step change from lower to higher resolution startpos iy ix iy ix dir nxt1 nxt2 nxt3 dir endpos halfstep 1/8 th step change from higher to lower resolution startpos figure 12. nxt?step mode synchronization left : change from lower to higher resolution. the left?hand side depicts the ending half?step position during which a new step mode resolution was programmed. the right?hand side diagram shows the effect of subsequent nxt commands on the micro?step position. right : change from higher to lower resolution. the left?hand side depicts the ending micro?step position during which a new step mode resolution was programmed. the right?hand side diagram shows the effect of subsequent nxt commands on the half?step position. note : it is advised to reduce the micro?stepping resolution only at micro?step positions that overlap with desired micro?step positions of the new resolution. programmable peak?current the amplitude of the current waveform in the motor coils (coil peak current = i max ) is adjusted by means of an spi parameter ?cur[4:0]? (see t able 14 spi control parameter overview). whenever this parameter is changed, the coil?currents will be updated immediately at the next pwm period. figure 13 presents the peak?current and current ratings in conjunction to the current setting cur[4:0]. 81522 31 0 cur[4:0] peak current current range 0 cur[4 :0] = 0 ?> 8 current range 1 cur[4:0] = 9 ?> 15 current range 2 cur [4:0 ] = 16 ?> 22 current range 3 cur[ 4:0 ] = 23 ?> 31 328 ma 654 ma 1.26 a 3.02 a figure 13. programmable peak?current overview
amis?30532 www. onsemi.com 17 speed and load angle output the sla?pin provides an output voltage that indicates the level of the back?e.m.f. voltage of the motor. this back?e.m.f. voltage is sampled during every so?called ?coil current zero crossings?. per coil, two zero?current positions exist per electrical period, yielding in total four zero?current observation points per electrical period. figure 14. principle of bemf measurement v bemf zoom t v bb v coil voltage transient next m icr o ? step previous m icro ?step coil current zero crossing current decay zero current t t i coil i coil |v bemf | because of the relatively high recirculation currents in the coil during current decay, the coil voltage v coil shows a transient behavior. as this transient is not always desired in application software, two operating modes can be selected by means of the bit (see ?sla?transparency? in see spi control parameter overview). the sla pin shows in ?transparent mode? full visibility of the voltage transient behavior. this allows a sanity?check of the speed?setting versus motor operation and characteristics and supply voltage levels. if the bit ?slat? is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the sla?pin. because the transient behavior of the coil voltage is not visible anymore, this mode generates smoother back e.m.f. input for post?processing, e.g. by software. in order to bring the sampled back e.m.f. to a descent output level (0 v to 5 v), the sampled coil voltage v coil is divided by 2 or by 4. this divider is set through an spi bit . (see spi control parameter overview) the following drawing illustrates the operation of the sla?pin and the transparency?bit. ?pwmsh? and ?i coil = 0? are internal signals that define together with slat the sampling and hold moments of the coil voltage.
amis?30532 www. onsemi.com 18 pwmsh icoil=0 slat sla? pin slat=0 => sla? pin is not ?transparent? during v bemf sampling @ coil current zero crossing. sla?pin is updated when leaving current?less state. slat=1 => sla?pin is ?transparent? during v bemf sampling @ coil current zero crossing. sla? pin is updated ?real? time?. last sample is retained retain last sample previous output is kept at sla pin buf ssh sh ch csh slat not(icoil=0) icoil=0 pwmsh sla?pin v coil div2 div4 v bemf t t v coil figure 15. timing diagram of sla?pin warning, error detection and diagnostics feedback thermal warning and shutdown when junction temperature rises above t tw , the thermal warning bit < tw > is set (table 16 spi status registers address sr0). if junction temperature increases above thermal shutdown level, then the circuit goes in ?thermal shutdown? mode (< tsd >) and all driver transistors are disabled (high impedance) (see t able 16 spi status registers address sr2). the conditions to reset flag < tsd > is to be at a temperature lower than t tw and to clear the < tsd > flag by reading it using any spi read command. overcurrent detection the overcurrent detection circuit monitors the load current in each activated output stage. if the load current exceeds the overcurrent detection threshold, then the over?current flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit. each driver transistor has an individual detection bit in (see t able 16 spi status registers address sr1 and sr2: < ovcxij > and < ovcyij >). error condition is latched and the microcontroller needs to clean the status bits to reactivate the drivers. note : successive reading the spi statusregisters 1 and 2 in case of a short circuit condition, may lead to damage to the drivers. open coil/current not reached detection open coil detection is based on the observation of 100% duty cycle of the pwm regulator. if in a coil 100% duty cycle is detected for longer than 200 ms then the related driver transistors are disabled (high?impedance) and an appropriate bit in the spi status register is set (< openx > or < openy >). (table 16) when the resistance of a motor coil is very large and the supply voltage is low, it can happen that the motor driver is not able to deliver the requested current to the motor. under these conditions the pwm controller duty cycle will be 100% and after 200 ms the error pin and < openx >, < openy > will flag this situation (motor current is kept alive). this feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil?current or else the coil current should be reduced. charge pump failure the charge pump is an important circuit that guarantees low r ds(on) for all drivers, especially for low supply
amis?30532 www. onsemi.com 19 voltages. if supply voltage is too low or external components are not properly connected to guarantee r ds(on) of the drivers, then the bit is set (table 16). also after por the charge pump voltage will need some time to exceed the required threshold. during that time will be set to ?1?. error output this is a digital output to flag a problem to the external microcontroller. the signal on this output is active low and the logic combination of: not(errb) = or or or or or logic supply regulator amis?30532 has an on?chip 5 v low?drop regulator with external capacitor to supply the digital part of the chip, some low?voltage analog blocks and external circuitry. the voltage is derived from an internal bandgap reference. to calculate the available drive?current for external circuitry, the specified i load should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. see table 5 dc parameters. power?on reset (por) function the open drain output pin por /wd provides an ?active low? reset for external purposes. at power?up of amis?30532, this pin will be kept low for some time to reset for example an external microcontroller. a small analog filter avoids resetting due to spikes or noise on the v dd supply. t pu t por t rf vbb v ddh vdd v ddl t pd bit (t able 13: spi control registers (all spi control registers have read/write access and default to ?0? after power?on or hard reset.)). once this bit has been set to ?1? (watchdog enable), the microcontroller needs to re?write this bit to clear an internal timer before the watchdog timeout interval expires. in case the timer is activated and wden is acknowledged too early (before t wdpr ) or not within the interval (after t wdto ), then a reset of the microcontroller will occur through por /wd pin. in addition, a warm/cold boot bit < wd > is available (see tables 16 and 17) for further processing when the external microcontroller is alive again. clr pin (=hard reset) logic 0 on clr pin allows normal operation of the chip. to reset the complete digital inside amis?30532, the input clr needs to be pulled to logic 1 during minimum time given by t clr . (table 6 ac parameters). this reset function clears all internal registers without the need of a power?cycle, except in sleep mode. the operation of all analog circuits is depending on the reset state of the digital, charge pump remains active. logic 0 on clr pin resumes normal operation again. the voltage regulator remains functional during and after the reset and the por /wd pin is not activated. watchdog function is reset completely. sleep mode the bit < slp > in spi control register 2 (see table 12) is provided to enter a so?called ?sleep mode?. this mode allows reduction of current?consumption when the motor is not in operation. the effect of sleep mode is as follows: ? the drivers are put in hiz ? all analog circuits are disabled and in low?power mode ? all internal registers are maintaining their logic content ? nxt and dir inputs are forbidden ? spi communication remains possible (slight current increase during spi communication) ? reset of chip is possible through clr pin
amis?30532 www. onsemi.com 20 ? oscillator and digital clocks are silent, except during spi communication the voltage regulator remains active but with reduced current?output capability (i loadslp ). the watchdog timer stops running and it?s value is kept in the counter. upon leaving sleep mode, this timer continues from the value it had before entering sleep mode. normal operation is resumed after writing logic ?0? to bit . a start?up time is needed for the charge pump to stabilize. after this time, nxt commands can be issued. t pu por/wd pin t por vbb v ddh vdd t t t dspi enable wd acknowledge wd wd timer t por t wdrd = t wdpr or = t wdto >t wdpr and < t wdto t t t wdto figure 17. watchdog timing diagram note : t dspi is the time needed by the external microcontroller to shift?in the bit after a power?up. the duration of the watchdog timeout interval is programmable through the wdt[3:0] bits (see also table 13: spi control registers (all spi control registers have read/write access and default to ?0? after power?on or hard reset.). the timing is given in table 12 below. table 12. watchdog timeout interval as function of wdt[3.0] index wdt[3:0] t wdto (ms) index wdt[3:0] t wdto (ms) 0 0000 32 8 1000 288 1 0001 64 9 1001 320 2 0010 96 10 1010 352 3 0011 128 11 1011 384 4 0100 160 12 1100 416 5 0101 192 13 1101 448 6 0110 224 14 1110 480 7 0111 256 15 1111 512
amis?30532 www. onsemi.com 21 spi interface the serial peripheral interface (spi) allows an external microcontroller (master) to communicate with amis?30532. the implemented spi block is designed to interface directly with numerous micro?controllers from several manufacturers. amis?30532 acts always as a slave and can?t initiate any transmission. the operation of the device is configured and controlled by means of spi registers which are observable for read and/or write from the master. spi transfer format and pin signals during a spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (clk) synchronizes shifting and sampling of the information on the two serial data lines (do and di). do signal is the output from the slave (amis?30532), and di signal is the output from the master. a chip select line (cs ) allows individual selection of a slave spi device in a multiple?slave system. the cs line is active low. if amis?30532 is not selected, do is pulled up with the external pull up resistor. since amis?30532 operates as a slave in mode 0 (cpol = 0; cpha = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. the master spi port must be configured in mode 0 too, to match this operation. the spi clock idles low between the transferred bytes. the diagram below is both a master and a slave timing diagram since clk, do and di pins are directly connected between the master and the slave. figure 18. timing diagram of an spi transfer ??? ??? ??? ???? ???? di msb clk 1 2 3 4 5 6 7 8 cs do # clk cycle msb lsb lsb 6 543 21 6 543 21 note: at the falling edge of the eight clock pulse the data?out shift register is updated with the content of the addressed inte rnal spi register. the internal spi registers are updated at the first rising edge of the amis?30532 system clock when cs = high transfer packet serial data transfer is assumed to follow msb first rule. the transfer packet contains one or more 8?bit characters (bytes). lsb data command and spi register address cmd2 cmd1 cmd0 addr4 addr3 addr2 addr1 addr0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb byte 1 byte 2 command spi register address figure 19. spi transfer packet byte 1 contains the command and the spi register address and indicates to amis?30532 the chosen type of operation and addressed register. byte 2 contains data, or sent from the master in a write operation, or received from amis?30532 in a read operation.
amis?30532 www. onsemi.com 22 two command types can be distinguished in the communication between master and amis?30532: ? read from spi register with address addr[4:0]: cmd2 = ?0? ? write to spi register with address addr[4:0]: cmd2 = ?1? read operation if the master wants to read data from status or control registers, it initiates the communication by sending a read command. this read command contains the address of the spi register to be read out. at the falling edge of the eight clock pulse the data?out shift register is updated with the content of the corresponding internal spi register. in the next 8?bit clock pulse train this data is shifted out via do pin. at the same time the data shifted in from di (master) should be interpreted as the following successive command or dummy data. cs do data from addr 1 old data or not valid data data data from previous command or not valid after por or reset di read data from addr 1 command or dummy command figure 20. single read operation where data from spi register with address 1 is read by the master registers are updated with internal status at the rising edge of the internal amis?30532 clock when cs = 1 all 4 status registers (see spi registers) contain 7 data bits and a parity check bit the most significant bit (d7) represents a parity of d[6:0]. if the number of logical ones in d[6:0] is odd, the parity bit d7 equals ?1?. if the number of logical ones in d[6:0] is even then the parity bit d7 equals ?0?. this simple mechanism protects against noise and increases the consistency of the transmitted data. if a parity check error occurs it is recommended to initiate an additional read command to obtain the status again. also the control registers can be read out following the same routine. control registers don?t have a parity check. the cs line is active low and may remain low between successive read commands as illustrated in figure 22. there is however one exception. in case an error condition is latched in one of status registers (see spi registers) the errb pin is activated. (see section error output). this signal flags a problem to the external microcontroller. by reading the status registers information about the root cause of the problem can be determined. after this read operation the status registers are cleared. because the status registers and errb pin (see spi registers) are only updated by the internal system clock when the cs line is high, the master should force cs high immediately after the read operation. for the same reason it is recommended to keep the cs line high always when the spi bus is idle. write operation if the master wants to write data to a control register it initiates the communication by sending a write command. this contains the address of the spi register to write to. the command is followed with a data byte. this incoming data will be stored in the corresponding control register after cs goes from low to high! amis?30532 responds on every incoming byte by shifting out via do the data stored in the last received address. it is important that the writing action (command ? address and data) to the control register is exactly 16 bits long. if more or less bits are transmitted the complete transfer packet is ignored. a write command executed for a read?only register (e.g. status registers) will not affect the addressed register and the device operation. because after a power?on?reset the initial address is unknown the data shifted out via do is not valid.
amis?30532 www. onsemi.com 23 di cs do write data to addr 3 new data for addr 3 old data from addr 3 old data or not valid command data data data from previous command or not valid after por or reset data figure 21. single write operation where data from the master is written in spi register with address 3 the new data is written into the corresponding internal register at the rising edge of cs examples of combined read and write operations in the following examples successive read and write operations are combined. in figure 22 the master first reads the status from register at addr4 and at addr5 followed by writing a control byte in control register at addr2. note that during the write command the old data of the pointed register is returned at the moment the new data is shifted in. figure 22. 2 successive read commands followed by a write command di cs do read data from addr4 old data or not valid command data data data from previous command or not valid after por or reset command command data data data data from addr4 read data from addr5 data from addr5 write data to addr 2 new data for addr2 old data from addr2 registers are updated with the internal status at the rising edge of the internal amis?30532 clock when cs = 1 the new data is written into the correspondinginternal register at the rising edge of cs after the write operation the master could initiate a read back command in order to verify the data correctly written as illustrated in figure 23. during reception of the read command the old data is returned for a second time. only after receiving the read command the new data is transmitted. this rule also applies when the master device wants to initiate an spi transfer to read the status registers. because the internal system clock updates the status registers only when cs line is high, the first read out byte might represent old status information.
amis?30532 www. onsemi.com 24 di cs do write data to addr2 old data or not valid command data data data from previous command or not valid after por or reset command data data data old data from addr2 new data for addr2 old data from addr2 read data from addr2 command or dummy new data from addr2 figure 23. a write operation where data from the master is written in spi register with address 2 followed by a read back operation to confirm a correct write operation registers are updated with the internal status at the rising edge of cs the new data is written into the correspondinginternal register at the rising edge of cs note: the internal data?out shift buffer of amis?30532 is updated with the content of the selected spi register only at the last (every eight) falling edge of the clk signal (see spi transfer format and pin signals). as a result, new data for transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data. table 13. spi control registers (all spi control registers have read/write access and default to ?0? after power?on or hard reset) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 wr (00h) data wden wdt[3:0] ? ? ? cr0 (01h) data sm[2:0] cur[4:0] cr1 (02h) data dirctrl nxtp ? ? pwmf pwmj emc[1:0] cr2 (03h) data moten slp slag slat ? ? ? ? cr2 (08h) data m[1:0] strb[1:0] ? strc stre[1:0] where : r/w read and write access reset: status after power-on or hard reset
amis?30532 www. onsemi.com 25 table 14. spi control parameter overview symbol description status value dirctrl controls the direction of rotation (in combination with logic level on input dir) = 0 = 0 cw motion (note 15) = 1 ccw motion (note 15) = 1 = 0 ccw motion (note 15) = 1 cw motion (note 15) nxtp selects if nxt triggers on rising or falling edge = 0 trigger on rising edge = 1 trigger on falling edge emc[1:0] turn on ? turn?of f slopes of motor driver (note 14) 00 very fast 01 fast 10 slow 11 very slow slat speed load angle transparency bit = 0 sla is transparent = 1 sla is not transparent slag speed load angle gain setting = 0 gain = 0.5 = 1 gain = 0.25 pwmf enables doubling of the pwm frequency (note 14) = 0 default frequency = 1 double frequency pwmj enables jittery pwm = 0 jitter disabled = 1 jitter enabled sm[2:0] stepmode 000 1/32 micro ? step 001 1/16 micro ? step 010 1/8 micro ? step 011 1/4 micro ? step 100 compensated half step 101 uncompensated half step 110 full step 111 n.a. slp enables sleep mode = 0 active mode = 1 sleep mode moten activates the motor driver outputs = 0 drivers disabled = 1 drivers enabled m[1:0] pwm mode control 00 default pwm control 01 dcmin mode 1 10 dcmin mode 2 11 dcmin mode 3 strb[1:0] pwm strobe b control: don mask comparator time (note 16) 00 4 pwm clock cycles 01 8 pwm clock cycles 10 12 pwm clock cycles 11 19 pwm clock cycles strc pwm strobe c control: switch time top/bottom regulation = 0 86% duty cycle pwm regulator = 1 75% duty cycle pwm regulator stre[1:0] pwm strobe e control: compensation bridge active time (note 16) 00 4 pwm clock cycles 01 8 pwm clock cycles 10 12 pwm clock cycles 11 19 pwm clock cycles 14. the typical values can be found in table 5: dc parameters and in table 6: ac parameters 15. depending on the wiring of the motor connections 16. the duration is depending on the selected pwm frequency
amis?30532 www. onsemi.com 26 cur[4:0] selects imcmax peak. this is the peak or amplitude of the regulated current waveform in the motor coils. table 15. spi control parameter overview cur[4:0] current range (note 18) index cur[4:0] current (ma) (note 17) current range (note 18) index cur[4:0] current (ma) (note 17) 0 0 00000 66 2 16 10000 735 1 00001 135 17 10001 800 2 00010 189 18 10010 883 3 00011 200 19 10011 975 4 00100 221 20 10100 1077 5 00101 244 21 10101 1189 6 00110 269 22 10110 1255 7 00111 297 3 23 10111 1485 8 01000 328 24 11000 1625 1 9 01001 366 25 11001 1767 10 01010 400 26 11010 1950 11 01011 442 27 11011 2153 12 01100 488 28 11100 2378 13 01101 538 29 11101 2552 14 01110 594 30 11110 2775 15 01111 654 31 11111 3015 17. typical current amplitude at t j = 125 c 18. reducing the current over different current ranges might trigger overcurrent detection. see dedicated application note for s olutions spi status register description all 4 spi status registers have read access and are default to ?0? after power-on or hard reset. table 16. spi status registers address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r r r r r r r r reset 0 0 0 0 0 0 0 0 sr0 (04h) data is not latched par tw cpfail wd openx openy ? ? sr1 (05h) data is latched par ovcxpt ovcxpb ovcxnt ovcxnb ? ? ? sr2 (06h) data is latched par ovcypt ovcypb ovcyynt ovcynb tsd ? ? sr3 (07h) data is not latched par msp[6:0] where : r read only mode access reset status after power-on or hard reset par parity check
amis?30532 www. onsemi.com 27 table 17. spi status flags overview mnemonic flag length (bit) related spi register comment reset state cpfail charge pump failure 1 status register 0 ?0? = no failure ?1? = failure: indicates that the charge pump does not reach the required voltage level. note 1 ?0? msp[6:0] micro?step position 7 status register 3 translator micro step position ?0000000? openx open coil x 1 status register 0 ?1? = open coil detected ?0? openy open coil y 1 status register 0 ?1? = open coil detected ?0? ovcxnb ov er current on x h?bridge; mot xn terminal; b ottom tran. 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor xn?terminal ?0? ovcxnt ov er current on x h?bridge; mot xn terminal; t op transist. 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor xn?terminal ?0? ovcxpb ov er current on x h?bridge; mot xp terminal; b ottom tran. 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor xp?terminal ?0? ovcxpt ov er current on x h?bridge; mot xp terminal; t op transist. 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor xp?terminal ?0? ovcynb ov er current on y h?bridge; mot yn terminal; b ottom tran. 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor yn?terminal ?0? ovcynt ov er current on y h?bridge; mot yn terminal; t op transist. 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor yn?terminal ?0? ovcypb ov er current on y h?bridge; mot yp terminal; b ottom tran. 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor yp?terminal ?0? ovcypt ov er current on y h?bridge; mot yp terminal; t op transist. 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor yp?terminal ?0? tsd thermal shutdown 1 status register 2 ?0? tw thermal warning 1 status register 0 ?0? wd watchdog event 1 status register 0 ?1? = watchdog reset after time?out ?0? note: wd ? this bit indicates that the watchdog timer has not been cleared properly. if the master reads that wd is set to ?1? a fter reset, it means that a watchdog reset occurred (warm boot) instead of por (cold boot). wd bit will be cleared only when the master writes ?0? to wden bit. table 18. ordering information part no. peak current temperature range package shipping ? amis30532c5321rg 1600 ma ?40 c to 125 c nqfp?32 (7 x 7 mm) (pb?free) tape & reel amis30532c5321g 1600 ma ?40 c to 125 c nqfp?32 (7 x 7 mm) (pb?free) tube ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
amis?30532 www. onsemi.com 28 package dimensions nqfp?32, 7x7 case 560aa issue o
amis?30532 www. onsemi.com 29 package dimensions nqfp?32, 7x7 case 560aa issue o on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 amis?30532/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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